In the past, electronic devices use various types of clock generation circuits in order to generate various kinds of clock signals. For example, a clock generation circuit having an NCO (Numerical Controlled Oscillator), a loop filter, and a DLL (Delay Locked Loop) has been suggested (for example, see PTL 1). This clock generation circuit outputs an overflow signal by changing the count value of the NCO on the basis of phase information. By using this overflow signal as a clock signal, a clock signal of any given average frequency can be attained. In this clock generation circuit, the amount of jitter is reduced in the overflow signal given by the NCO by further increasing the time precision with a DLL in a later stage. In this clock generation circuit, a loop filter can be constituted by a digital circuit for a low frequency reference clock signal, and therefore, as compared with the case where an analog filter is used, the loop band can be reduced with a smaller size of implementation area.